Answers Database
SYNPLIFY: How to infer the BUFGDLL cell for Virtex using the xc_clockbuftype attribute?
Record #688
Product Family: Software
Product Line: Synplicity
Product Part: Synplify
Product Version: 5.0
Problem Title:
SYNPLIFY: How to infer the BUFGDLL cell for Virtex using the xc_clockbuftype attribute?
Problem Description:
Urgency: Sandard
General Description:
How to infer the BUFGDLL cell for Virtex using the
xc_clockbuftype attribute?
A Virtex only attribute, first introduced in Synplify 5.1.2, which
specifies that a clock port is to use the BUFGDLL macro.
The BUFGDLL is a special purpose clock delay locked loop
buffer for clock skew management. It is provided as a user
convenience for the most frequently used configuration of
elements for clock skew management. It consists of an IBUFG
followed by a CLKDLL followed by a BUFG.
NOTE: Tested with Synplify 5.1.5a
Solution 1:
// Verilog
module bufgdll_ex (d, clk, rst, q);
input [1:0] d;
input clk /* synthesis xc_clockbuftype="BUFGDLL" */;
input rst;
output [1:0] q;
reg [1:0] q;
always @(posedge clk or posedge rst)
if (rst)
q <= 2'b0;
else
q <= d;
endmodule
Solution 2:
-- VHDL library IEEE;
library IEEE;
use IEEE.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity bufgdll_ex1 is
port (D : in STD_LOGIC_VECTOR (1 downto 0);
CLK, RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (1 downto 0));
attribute xc_clockbuftype of CLK : signal is "BUFGDLL";
end bufgdll_ex1;
architecture XILINX of bufgdll_ex1 is
begin
process (RST, CLK)
begin
if (RST = '1') then
Q <= "00";
elsif rising_edge(CLK) then
Q <= D;
end if;
end process;
end XILINX;
Solution 3:
# SDC
define_attribute <port_name> xc_clockbuftype {BUFGDLL}
End of Record #688 - Last Modified: 08/04/99 11:13 |
