Answers Database
Synopsys: XC5200: clock inversion is implemented in a function generator, not at the flip-flop.
Record #857
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Compiler
Problem Title:
Synopsys: XC5200: clock inversion is implemented in a function generator, not at the
flip-flop.
Problem Description:
When Synopsys performs mapping for 5200 designs, the "replace_fpga" command is not required. Instea
d of writing to gates, the compiler writes EQN records in the .sxnf file to map combinatorial logic
to function generators. This means that simple inversions or events on the negative clock-edge in y
our code result not in an INV record in the .sxnf, but rather in an EQN record with the equation's b
eing equal to ~I0.
Since the Xilinx tools do not see this as an absorbable inverter, it is placed in a separate functio
n generator (just as the EQN statement mandates). Thus the clock inversion for flip-flops triggered
on the negative edge of the clock takes place in a separate Logic Cell, rather than directly at the
flip-flop's clock pin.
Solution 1:
Either of the solutions below will work:
1. After compiling in Synopsys, run the command "replace_fpga -force". This will put everything in
terms of gates. You will lose all of Synopsys' mapping directives, leaving all mapping up to the X
ilinx core tools. Do this before writing out the .sxnf file.
-OR-
2. Manually edit the .xff file, deleting the offending EQN component(s)
and modifying the appropriate PIN records to include an INV attribute.
This is really only a solution for specific cases
such as an inverted GSR pin to STARTUP or a negative edge clock.
Below is an example of a falling-edge-clocked flip-flop correctly written in XNF format:
SYM, out_reg/$1I13, DFF, HIERG=2, LIBVER=2.0.0
PIN, C, I, n34, , INV
PIN, D, I, n33
PIN, Q, O, n32
End of Record #857 - Last Modified: 05/30/96 14:21 |
