Answers Database
Specifying an FDCE in VIEWsynthesis
Record #881
Product Family: Software
Product Line: ViewLogic
Product Part: Viewsynthesis
Product Version: 7.2
Problem Title:
Specifying an FDCE in VIEWsynthesis
Problem Description:
There are two ways to specify a register with Clock Enable line.
Solution 1:
Instantiation:
FDCE has a hidden pin ("GSR" for the xc4000 and "GR" for the
xc3000 and xc5200) which needs to be listed in the component
definition.
Example for a xc4000 device:
library synth;
use synth.stdsynth.all;
entity sw7_gsr is
port (CLK: in STD_LOGIC;
CLKE: in STD_LOGIC;
CLEAR: in STD_LOGIC;
SW: in STD_LOGIC;
SWI: out STD_LOGIC);
end sw7_gsr;
architecture rtl of sw7_gsr is
component FDCE
port (CLR: in STD_LOGIC;
CE: in STD_LOGIC;
D : in STD_LOGIC;
C : in STD_LOGIC;
GSR: in STD_LOGIC; -- sneaky --
Q : out STD_LOGIC);
end component;
begin
fdcein: FDCE port map (CLEAR, CLKE, SW, CLK, '0', SWI);
end rtl;
Solution 2:
Behavioral description using Clock Enable with
AsynchronousReset
LIBRARY ieee;
USE ieee.std_logic_1164.all;
Entity sync IS
PORT(din, clk, clke, reset : IN std_logic;
dout : OUT std_logic);
END;
ARCHITECTURE behav OF sync IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL (prising(clk) OR reset = '1');
IF reset='1' THEN
dout <='1';
ELSE
IF clke ='1' THEN
dout <= din;
END IF;
END IF;
END PROCESS;
END behav;
End of Record #881 - Last Modified: 01/09/97 10:46 |
