Answers Database
Foundation XVHDL, F6.x: Instantiating I/O buffers causes XNFPREP error 3530
Record #954
Product Family: Software
Product Line: Metamor
Product Part: Foundation XVHDL
Product Version: 2.34
Problem Title:
Foundation XVHDL, F6.x: Instantiating I/O buffers causes XNFPREP error 3530
Problem Description:
Urgency: Standard
General Description:
During design implementation, the Optimize step fails. The
DRC Report lists the following error:
XNFPREP: ERROR 3530
The signal 'U1_i' is illegally connected to I/O symbols
as shown below:
<lists of symbol pins corresponding to I/O and internal
logic>
This error may occur if I/O components were instantiated in
VHDL source code. The XVHDL compiler automatically adds I/O
buffers and flip-flops to all top-level entity ports. If an
I/O component is instantiated, XVHDL inserts another I/O
buffer in front of the instantiated component, producing an
invalid netlist.
Solution 1:
To specify a BUFG on a clock port, use the Xilinx_BUFG
attribute:
attribute Xilinx_BUFG : boolean;
attribute Xilinx_BUFG of CLOCK : signal is true;
To specify an XC7300 BUFFOE on an output enable port, use the
following syntax:
attribute Xilinx_BUFG : boolean;
attribute Xilinx_BUFG of OUTEN : signal is true;
attribute property : string;
attribute property of OUTEN : signal is "SCHNM=BUFFOE";
Compile the design as a Chip. XVHDL will insert the
appropriate global buffer on the port instead of an IBUF.
To specify other I/O buffers, registers, or latches, compile
the design as a Macro, place the symbol on a top-level
schematic, and add all I/O components using the schematic
editor.
See also (Xilinx Solution 1373), (Xilinx Solution 1374), and
(Xilinx Solution 1375).
End of Record #954 - Last Modified: 01/03/00 10:58 |
