Answers Database
Defining pin attributes/locations for a VHDL code using Viewsynthesis
Record #970
Product Family: Software
Product Line: ViewLogic
Product Part: Viewsynthesis
Product Version: 5.0.2x
Problem Title:
Defining pin attributes/locations for a VHDL code using Viewsynthesis
Problem Description:
This describes how some attributes can be added to the IO
pins using Viewsynthesis.
Solution 1:
A DESIGN.FPN file needs to be created in the project directory
with the following commands:
| a comment
| Define location TOP-RIGHT for pin RST
bufatt RST loc=tr
| Define location p13 and FAST output for pin outt[7]
bufatt outt[7] loc=p13, fast
Note that the line:
bufatt RST loc=tr
causes the RST pad to be located "tr" (or "top right").
Note that the line:
bufatt outt[7] loc=p13,fast
ends up as attributes on the outt[7] pad -- it is to be
located at pad p13, and to be a "fast" slew-rate pad.
End of Record #970 - Last Modified: 10/25/96 09:31 |
