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MODELSIM VLOG (MTI): Running Verilog simulation
Record #1078
Product Family: Software
Product Line: Model Technology
Product Part: Modelsim
Product Version: 5.2
Problem Title:
MODELSIM VLOG (MTI): Running Verilog simulation
Problem Description:
Urgency: Standard
General Description:
How to run simulation with Modelsim VLOG (Verilog simulation)?
There are two methods to run simulation with Modelsim Vlog:
- Using library source files with compile-time options (similar to Verilog-XL)
- Using shared pre-compiled libraries
Please see (Xilinx Solution 2561) on how to compile the Alliance 2.1i
libraries for Modelsim Vlog.
Solution 1:
Using library source files with compile-time options (similar to Verilog-XL):
Depending on the makeup of the design (LogiBlox, Xilinx instantiated
primitives, or Coregen components), for RTL simulation, specify the
following at the command-line:
vlog -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/simprims \
-y <path_coregen>/XilinxCoreLib +libext+.v $XILINX/verilog/src/glbl.v \
-incr -R <testfixture>.v <design>.v
The $XILINX/verilog/src/unisims area contains the Unified components
for RTL simulation. The $XILINX/verilog/src/simprims area contains
generic simulation primitives for LogiBlox. The XilinxCoreLib area contains
the Coregen components for RTL simulation. Please see
(Xilinx Solution 7859) for instructions on extracting this library.
The -incr option enables incremental compilation. The -R option causes
vsim to be invoked with the simulation arguments and top-level modules.
For timing simulation or post-Ngd2ver, the Simprims-based libraries are used.
Specify the following at the command-line:
vlog -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v \
+libext+.v <testfixture>.v <design>.v -incr -R
Solution 2:
Using shared pre-compiled libraries:
Simulation Libraries have to be compield to <mapped_compiled_lib_dir>
before using Modelsim Vlog. See (Xilinx Solution 2561) for instruction on
how to compile the Xilinx Verilog libraries.
Depending on the makeup of the design (LogiBlox, Xilinx instantiated
primitives, or Coregen components) for RTL simulation, specify the
following at the command-line:
vlog $XILINX/verilog/src/glbl.v <testfixture>.v <design>.v \
-incr -R -L unisims_ver -L simprims_ver -L xilinxcorelib_ver -
The unisims_ver area contains the Unified components for RTL
simulation. The simprims_ver area contains generic simulation
primitives for LogiBlox. The xilinxcorelib_ver area contains the
Coregen components for RTL simulation. Please see
(Xilinx Solution 7859) for instructions on extracting this library.
The -incr option enables incremental compilation. The -R option
causes vsim to be invoked with the simulation arguments and
top-level modules. The -L <mapped_compiled_lib_dir> option
provides VSIM with a library to search for design units instantiated
from Verilog.
For timing simulation or post-Ngd2ver, the Simprims-based libraries
are used. Specify the following at the command-line:
vlog $XILINX/verilog/src/glbl.v <testfixture>.v <design>.v \
-incr -R -L simprims_ver -
End of Record #1078 - Last Modified: 12/16/99 13:51 |
