Answers Database How to add XACT-Performance (Timespec) constraints to my CST file Record #1331 Product Family: Software Product Line: FPGA Implementation Product Part: Timing Analyzer Product Version: 6.0 Problem Title: How to add XACT-Performance (Timespec) constraints to my CST file Problem Description: How do I add XACT-Performance (Timespec) constraints to my CST file? Solution 1: Putting XACT-Performance specifications in CST files is relatively straightforward. Let's say you have the following timing specifications. If placed directly on the schematic, these would be attributes attached to the TIMESPECsymbol: TIMESPEC ======== TS_PIPELINE = FROM:FFS:TO:FFS=40MHZ TS_GETIN = FROM:ENTRANCE:TO:FFS=20NS TS_GETOUT = FROM:FFS:TO:EXIT=TS_GETOUT*.75 (ENTRANCE and EXIT are user-defined timing names.) If you wanted to put thes in your (design).cst file instead, the format would be:     timespec="TS_PIPELINE=FROM:FFS:TO:FFS=25";     timespec="TS_GETIN=FROM:ENTRANCE:TO:FFS=20";     timespec="TS_GETOUT=FROM:FFS:TO:EXIT=15"; Note that all specifications, whether they be given in time or frequency, must be converted to nanoseconds. The CST file is case-insensitive and requires a semicolon to terminate each line. You can do TIMEGRP attributes in a similar way. For example:     TIMEGRP     =======     MY_COUNTER = THIS_GROUP:THAT_GROUP     MY_DRIVERS = THESE_PADS:THOSE_PADS     MY_REGISTER = FFS(SHIFT_OUT*) would, in the (design).cst file, be:     timegrp="MY_COUNTER=THIS_GROUP:THAT_GROUP";     timegrp="MY_DRIVERS=THESE_PADS:THOSE_PADS";     timegrp="MY_REGISTER=FFS(SHIFT_OUT*)"; You can also combine timespec and timegrp statements in the CST file. This is especially useful in HDL synthesis designs, where TNMs cannot be attached directly to elements of your design. Say you wanted to control the path between a counter and a register. The output of the counter is ADDRESS(7:0) while the output of the register is PIPEDATA(7:0). You may define two timegroups as such:     timegrp="ADDRESS_COUNT=FFS(ADDRESS*)";     timegrp="PIPESTAGE=FFS(PIPEDATA*)"; This has the same effect of adding TNM=ADDRESS_COUNT to all flip-flops in the counter, and of adding TNM=PIPESTAGE to all flip-flops in the register. Be careful that you do not inadvertently include unwanted signals in your timegroups when using wildcards. The first timegrp specification would include in the ADDRESS_COUNT group a flip-flop whose output signal was called "ADDRESS_ENABLE", if such a signal existed. Adjust   your signal names if necessary. Once you have the timing groups specified, the timespec is straightforward:     timespec="TS_ADDRLATCH=FROM:ADDRESS_COUNT:TO:PIPESTAGE=40"; IMPORTANT: Whenever you modify Timespec directives in a CST file, you MUST rerun XNFPrep; it is not sufficient to rerun only PPR:     xnfprep thiamin.xff thiamin.xtf    (xnfmap thiamin.xtf thiamin.map)     ppr thiamin.xtf/.map This is because PPR does not read timing constraints from the CST file; it relies on XNFPrep to write them into the XTF file. End of Record #1331 - Last Modified: 04/30/99 10:54

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