Answers Database Foundation XVHDL: Using pullups and pulldowns Record #1366 Product Family: Software Product Line: Metamor Product Part: Foundation XVHDL Problem Title: Foundation XVHDL: Using pullups and pulldowns Problem Description: Urgency: Standard General Description: Xilinx FPGAs contain internal pullup resistors in the I/O blocks (some also contain pulldowns). These components can be instantiated in your Foundation XVHDL code. **Note that this solution applies to the Metamor XVHDL compiler only. If using the Express HDL compiler, you may control the insertion of pullups via the Express Constraints GUI. Solution 1: The following example works only for pullups or pulldowns on OUTPUT pins. To use pullups/pulldowns on input pins, you must either place them on a schematic along with the VHDL module, or you may enable the pullup in the EPIC design editor. --Example of using Pullup library IEEE; use IEEE.std_logic_1164.all; entity IOB is port (IN1, CLOCK: in std_logic; OUT_PAD: out std_logic); attribute INHIBIT_BUF: boolean; attribute INHIBIT_BUF of OUT_PAD: signal is true; -- The INHIBIT_BUF attribute prevents the VHDL compiler from -- inferring an OBUF on the OUT_PAD port. This is necessary -- because we are going to instantiate an OBUF onto the port. end IOB; architecture PULLUP_EXAMPLE of IOB is component PULLUP     port ( O: out std_logic); end component; component OBUF     port (I: in std_logic;        O: out std_logic); end component; signal OUT_INTERNAL: std_logic;    -- This node is the input of the OBUF. begin process (CLOCK) begin    if CLOCK'event and CLOCK = '1' then      OUT_INTERNAL <= IN1;    end if; end process; U1: PULLUP port map (O => OUT_PAD);    -- Insert the pullup on the output of the OBUF. U2: OBUF port map (I => OUT_INTERNAL,               O => OUT_PAD); end PULLUP_EXAMPLE; End of Record #1366 - Last Modified: 01/03/00 10:55

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