Answers Database
CPLD: 9500: How do you use global clock nets?
Record #1489
Product Family: Hardware
Product Line: 9500
Product Part: 9500
Problem Title:
CPLD: 9500: How do you use global clock nets?
Problem Description:
Urgency: Standard
General Description:
How can I force the fitter to use the global clock resources?
Note: for the global clock buffers to be used there can be
no logic between the BUFG and the CLK pins of the flip flops.
Solution 1:
An internal clock signal can't be connected directly
to the input of a global clock buffer (BUFG). The signal must
first go through the dedicated Global Clock Pad, and then come
back in as the global clock through the BUFG.
To source a BUFG with an internally generated signal, use the
following configuration with and OBUF -> BUFG. This will
trick the fitter into using one of the dedicated PADS
associated with the global clock buffer.
Using this method will not allow you to use this pin on the
device.
Solution 2:
If the signal is generated external to the device, simply
use an IPAD -> BUFG for schematic.
This signal will be automatically routed to a Global Clock
Pin. If you want it to map to a specific GCLK pin, use
pinlocking to constrain the pin.
End of Record #1489 - Last Modified: 12/09/99 13:26 |
