Answers Database


SYNOPSYS: How to force a IOB NODELAY latch or flip-flop?


Record #1785

Product Family: Software

Product Line: Synopsys

Product Part: FPGA Compiler

Product Version: 1997.01

Problem Title:
SYNOPSYS: How to force a IOB NODELAY latch or flip-flop?


Problem Description:
Urgency: Standard

General Description:

XC4000e/ex/xl IOB flip-flops and latches have a delay block between the
external pin and the D input. The xc5200 IOB, also, provides a programmable
delay element to control input set-up time. This delay prevents any possible
hold-time violations if you have a clock signal that is also coming into the
device and clocking the input flip-flop or latch. You can remove this delay
with the NODELAY attribute. The NODELAY attribute decreases the setup-time
requirements and introduces a small hold-time.


Solution 1:

-- XC5200 - VHDL code
-- Instantiate an IBUF_F

library IEEE;
use IEEE.std_logic_1164.all;

entity ifd_ex is
     port (CLK, A, B: in STD_LOGIC;
        O: out STD_LOGIC);
end ifd_ex;

architecture xilinx of ifd_ex is

component IBUF_F
      port(I : in STD_LOGIC;
           O : out STD_LOGIC);
end component;

signal A_int : STD_LOGIC;
signal Q : STD_LOGIC;

begin
U0 : IBUF_F port map (I => A,
                 O => A_int);

process (CLK)
     begin
      if (CLK'event and CLK='1') then
          Q <= A_int;
      end if;
end process;

-- token logic
O <= Q and B;

end xilinx;


5200 -- Run-script for compiling VHDL Example:

PART = 5202pc84-3
TOP = ifd_ex

analyze -format vhdl TOP + ".vhd"
elaborate TOP

set_port_is_pad "*"
remove_attribute A port_is_pad
insert_pads

set_dont_touch U0

compile

set_attribute TOP "part" -type string PART

write -format xnf -hierarchy -output TOP + ".sxnf"



Solution 2:

// XC4000e/ex/xl - Verilog code
// Instantiate an IFD_F

module ifd_ex (CLK, A, B, O);

input A;
input B, CLK;
output O;

wire Q;

IFD_F U0 (.Q (Q), .D (A), .C (CLK));

//token logic
assign O = Q & B;

endmodule


XC4000e/ex/xl -- Run-script for compiling Verilog Example:

PART = 4003epc84-1
TOP = ifd_ex

read -format verilog TOP + ".v"

set_port_is_pad "*"
insert_pads

set_dont_touch U0

compile

replace_fpga

set_attribute TOP "part" -type string PART

write -format xnf -hierarchy -output TOP + ".sxnf"



Solution 3:

-- XC4000e/ex/xl - VHDL code
-- Instantiate an IFD_F

library IEEE;
use IEEE.std_logic_1164.all;

entity ifd_ex is
      port (CLK, A, B : in STD_LOGIC;
	    O	  : out STD_LOGIC);
end ifd_ex;

architecture xilinx of ifd_ex is

component IFD_F
       port(D, C : in STD_LOGIC;
         Q : out STD_LOGIC);
end component;

signal Q : STD_LOGIC;

begin
U0 : IFD_F port map (Q => Q,
                D => A,
                C => CLK);
-- token logic
O <= Q and B;

end xilinx;


XC4000e/ex/xl -- Run-script for compiling VHDL Example:

PART = 4003epc84-1
TOP = ifd_ex

analyze -format vhdl TOP + ".vhd"
elaborate TOP

set_port_is_pad "*"
insert_pads

set_dont_touch U0

compile

replace_fpga

set_attribute TOP "part" -type string PART

write -format xnf -hierarchy -output TOP + ".sxnf"



Solution 4:

// XC5200 - Verilog code
// Instantiate an IBUF_F

module ifd_ex (CLK, A, B, O);

input A ;
input B, CLK;
output O;

wire A_int;
reg Q;

IBUF_F U0 (.I (A), .O (A_int));

     always @ (posedge CLK)
     begin
        Q <= A_int;
     end

// token logic
assign O = Q & B;

endmodule


XC5200 -- Run-script for compiling Verilog Example:

PART = 5202pc84-3
TOP = ifd_ex

read -format verilog TOP + ".v"

set_port_is_pad "*"
remove_attribute A port_is_pad
insert_pads

set_dont_touch U0

compile

set_attribute TOP "part" -type string PART

write -format xnf -hierarchy -output TOP + ".sxnf"



Solution 5:

For xc4000e/ex/xl, you can remove the default delay by instantiating a
flip-flop or latch with a NODELAY attribute. Input flip-flops or latches
with an _F suffix have a NODELAY attribute assigned to the cell. For example,
the components IFD_F or ILD_1F remove this delay because these cells include a
NODELAY attribute.

However, since the xc5200 IOB does not include flip-flops or latches. The
xc5200 family provides direct connections from each IOB to the registers in the adjacent CLB in order to emulate IOB registers. You can remove the default
delay by instantiating a IBUF with a NODELAY attribute. The component IBUF_F
has the NODELAY attribute assigned to the cell.




End of Record #1785 - Last Modified: 04/13/99 09:33

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