Answers Database VERILOG-XL: Error! acc_replace_delays() [PLI-NOAPPREPMIPD] Error modifying MIPD: no XL loads on port Record #1793 Product Family: Software Product Line: Cadence Product Part: Verilog-XL Product Version: 2.5 Problem Title: VERILOG-XL: Error! acc_replace_delays() [PLI-NOAPPREPMIPD] Error modifying MIPD: no XL loads on port Problem Description: Urgency: Standard Problem Description: When using the Cadence's PLI routines to back-annotate a post layout file with Verilog-XL, the following error messages are generated: Error! acc_replace_delays() [PLI-NOAPPREPMIPD] Error modifying MIPD: no XL loads on port PR8.PLL.AGS "PR8.spec", 10: $tdc("PR8.option"); Error! acc_replace_delays() [PLI-NOAPPREPMIPD] Error modifying MIPD: non-XL loads on port PR8.PLL.BP "PR8.spec", 10: $tdc("PR8.option"); Error! acc_replace_delays() [PLI-NOAPPREPMIPD] Error modifying MIPD: non-XL loads on port PR8.PLL.FN "PR8.spec", 10: $tdc("PR8.option"); Error! acc_replace_delays() [PLI-NOAPPREPMIPD]       Error modifying MIPD: no XL loads on port       PR8.PLL.DYB       "PR8.spec", 10: $tdc("PR8.option"); Solution 1: The meaning of the error message "no XL loads on port PR8.PLL.AGS" and "no XL loads on port PR8.PLL.DYB" is that the ports AGS and DYB are floating. This violates a rule of SDF back annotation that the ports that are back-annotated must have to be connected to accelerable entities in Verilog-XL. In a similar manner, the port cannot be connected to a non-accelerated pin, unless through an acceleratable buffer. This is usually seen when using the Turbo algorithm which accelerates the simulation of behavioral constructs. End of Record #1793 - Last Modified: 06/17/99 15:11

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