Answers Database
XC9500: How to detemine low power mode timing (tLP, TLOGILP)
Record #1816
Product Family: Hardware
Product Line: 9500
Product Part: 9500
Problem Title:
XC9500: How to detemine low power mode timing (tLP, TLOGILP)
Problem Description:
This is a brief explanation of how to determine the path
timing of an XC9500 macrocell in low power mode.
For more detailed information, please consult the XC9500 Data
Sheets located on the Xilinx WWW site at:
http://www.xilinx.com/partinfo/db96.htm#CPLD
Solution 1:
In previous XC9500 Data Sheets there existed a parameter tLP,
the "Low power time delay adder." This parameter was added to
the tLOGI value to determine the low power logic delay.
In the most recent XC9500 Data Sheets, tLP has been replaced by
tLOGILP, which solely represents "Low power logic delay."
In effect, tLOGILP = tLP + tLOGI.
So, when determining path timing in low power mode, use
tLOGILP in place of tLOGI.
For example, the following path in low power mode would be
calculated as:
tPD = tIN + tLOGILP + tPDI + tOUT
9500 Timing Model
End of Record #1816 - Last Modified: 01/20/98 17:03 |
