Answers Database
UNISIMS/SIMPRIMS 2.1i: CLKDLL doesn't lock after RST is de-asserted
Record #1825
Product Family: Software
Product Line: FPGA Implementation
Product Part: Unisim
Product Version: n/a
Problem Title:
UNISIMS/SIMPRIMS 2.1i: CLKDLL doesn't lock after RST is de-asserted
Problem Description:
Urgency: Standard
General Description:
In the 2.1i UNISIMS/SIMPRIMS Verilog models, there is a bug
in the CLKDLL and CLKDLLHF models in which the LOCKED
signal never locks after the RST signal is de-asserted.
Solution 1:
This is fixed in Alliance 2.1i sp3 available at:
http://support.xilinx.com/support/techsup/sw_updates
End of Record #1825 - Last Modified: 11/18/99 10:55 |
