Answers Database
**Obsolete**Foundation Simulator: Unknown outputs on XBLOX or VHDL design
Record #1903
Product Family: Software
Product Line: Aldec
Product Part: Foundation Logic Simulator
Product Version: 1.19
Problem Title:
**Obsolete**Foundation Simulator: Unknown outputs on XBLOX or VHDL design
Problem Description:
Urgency: Standard
General Description:
During functional simulation the outputs of an XBLOX
component, or a VHDL macro containing inferred XBLOX
components, are unknown.
Solution 1:
This can happen if XBLOX is not being run prior to
simulation. The Project Manager may not detect the need to
run an XBLOX update. If this happens, the simulation netlist
will contain XBLOX components which are not simulatable.
To force an XBLOX update, delete the <design>.ALB and
<design>.ASX files, and run functional simulation again.
End of Record #1903 - Last Modified: 04/28/99 11:40 |
