Answers Database
Problem with pin mismatch, macro in Workview Office, xnf from Synplicity or FPGA Express
Record #2076
Product Family: Software
Product Line: ViewLogic
Product Part: Workview Office
Product Version: 7.5
Problem Title:
Problem with pin mismatch, macro in Workview Office, xnf from Synplicity or FPGA Express
Problem Description:
Urgency: Standard
Viewlogic writes out busses in xnf files with square brackets [] and both
Simplify 3.0 and FPGA Express 1.2/2.0 (and undoubtedly many others) write out
XNF files with angle brackets <>. Then viewing the nets on these buses,
Synplicity/Express bus nets will have angle brackets, but Viewlogic bus nets
will have no brackets at all.
This becomes a problem when you create a macro in Viewlogic that references
an .xnf file from Simplicity or Express. The convention mismatch will not
allow the sub-hierarchy to be merged by ngdbuild.
Solution 1:
The latest version of Workview Office (7.5) includes Synopsys FPGA Express 2.0.
Express replaces the Aurora synthesis tool, and has been integrated to work as
a module generator for the ViewDraw schematic capture tool. Therefore, this
issue does not exist with this package.
Contact Viewlogic (http://www.viewlogic.com ) to obtain this version of
Workview Office.
Solution 2:
The workaround is to manually change the bus names in the .XNF file(s).
Globally remove the angle bracket instances.
Therefore:
BUS<3>
becomes
BUS3
End of Record #2076 - Last Modified: 09/04/98 14:33 |
