Answers Database


M1 PLD_EDIF2TIM: Error: Cannot find library specified "SIMPRIMS"


Record #2100

Product Family: Software

Product Line: Mentor

Product Part: pld_edif2tim

Product Version: 1.3

Problem Title:
M1 PLD_EDIF2TIM: Error: Cannot find library specified "SIMPRIMS"


Problem Description:
Urgency: Hot

General Description:

PLD_EDIF2TIM exits with the following errors:

   //  Error: Cannot find library specified "/home/salma/dsprdo/SIMPRIMS"
   (from: Synthesis/EDIF Interface/Miscellaneous 15)
   //  Error: View "view_1" was not created successfully;
   //	      thus cannot instantiate "AND0". (from: Synthesis/EDIF
   Interface/Miscellaneous 1C)
   //  Note: Finding part "SIMPRIMS/x_and2" (from: Synthesis/EDIF
   Interface/Eddm Interface 81)
   //  Error: Could Not find the External part "SIMPRIMS/x_and2". (from:
   Synthesis/EDIF Interface/Miscellaneous 25)


Solution 1:

Timing simulations in Xilinx M1 use the simprim (simulation primitive)
library to model routed designs. For Mentor Graphics, these simulation
models are located in the $SIMPRIMS library. The $SIMPRIMS variable is
typically set to $LCA/simprims.

The EDIF file that PLD_EDIF2TIM is processing should reference this
simulation library as "$SIMPRIMS". However, in this situation, the library
is referenced as simply "SIMPRIMS" (without the dollar sign). This causes
ENRead (the Mentor EDIF reader that PLD_EDIF2TIM runs) to look in the
current directory for a SIMPRIMS subdirectory where it expects to find the
libraries.

To correct this, the EDIF file must be rewritten to reference the simprim
library as $SIMPRIMS. This is done with the vendor setting in NGD2EDIF:

    ngd2edif -v mentor banderas.nga

If you are using the Xilinx Design Manager/Flow Engine, go to the
Implementation Options Template. Under the Interface panel, change the
Simulation Data Options: Vendor setting to "Mentor". Rerun the Timing
stage of Flow Engine, re-export (Design Manager: Design -> Export) the
time_sim.edn file, and reprocess the EDN file through PLD_EDIF2TIM.




End of Record #2100 - Last Modified: 12/02/97 12:31

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!