Answers Database
Synopsys: How to specify slew rates in Synopsys FPGA Compiler or Design Compiler?
Record #2167
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Compiler
Problem Title:
Synopsys: How to specify slew rates in Synopsys FPGA Compiler or Design Compiler?
Problem Description:
Synopsys and Xilinx define slew rates in opposite terms. Synopsys uses slew control, whereas Xilinx
uses slew rate.
For example a Synopsys HIGH slew control is equivalent to a Xilinx SLOW slew rate. And by the same
definition, the Synopsys NONE or LOW slew control is equivalent to the Xilinx FAST slew rate.
Solution 1:
Use the following commands to your Compiler script:
set_pad_type -slewrate HIGH all_outputs ()
/* this sets the slew rate for all the outputs to SLOW */
set_pad_type -slewrate NONE {portnames}
/* this sets the slew rate for certain outputs to FAST */
For more information please refer to the Synopsys for FPGAs Interface/Tutorial Guide pages 5-9 to 5-
15.
NOTE: These script directives will not work for Virtex designs. The workaround is to instantitate
the appropriate buffers (i.e. OBUF_F) where needed and then modify your script to exclude those port
s in the set_port_is_pad stage.
End of Record #2167 - Last Modified: 05/21/99 14:43 |
