Answers Database
M1.3/M1.4/M1.5 CPLD: Fitter takes more than 200 Megs of RAM while fitting a design
Record #2243
Product Family: Software
Product Line: CPLD Implementation
Product Part: hitop
Product Version: 1.3
Problem Title:
M1.3/M1.4/M1.5 CPLD: Fitter takes more than 200 Megs of RAM while fitting a design
Problem Description:
Urgency: standard
General Description:
CPLD fitter may require more than 200 Megs of RAM while trying
to fit a design in a larger device such as 95216 or 95288.
The underlying cause would be the user's UCF file, if it
contains a lot of global timespecs which cause the fitter to
trace a large number of paths, greater than 100,000 in some
cases.
The CPLD fitter does not support MAX_PATHLIMIT option in the
constraints file which would be a solution.
Solution 1:
Use more specific Timespecs in your file as recommended by
Xilinx.
Example -
Instead of using a global timespec such as
TIMESPEC TS01 = FROM:FFS:TO:PADS:25ns;
use
TIMESPEC TS01 = FROM:Flip_Flop_1:TO:Pad_1:25ns;
Solution 2:
Turn off the Timespecs during the Fitting.
End of Record #2243 - Last Modified: 06/29/98 19:03 |
