Answers Database
Concept2xil causes NGDBUILD to issue "ERROR:based:48-..Duplicate port a in cell "alias_bit".
Record #2268
Product Family: Software
Product Line: Cadence
Product Part: concept2xil
Product Version: 2.16
Problem Title:
Concept2xil causes NGDBUILD to issue "ERROR:based:48-..Duplicate port a in cell "alias_bit".
Problem Description:
Urgency: standard
General Description:
NGDBUILD or Edif2NGD may issue the following error on a
Concept design which contains buses:
<output>
ERROR:based:48 - On or above line 371 in file "calc.edf":
Duplicate port a in cell "alias_bit". This likely means
that the EDIF netlist was improperly written. Please
contact the vendor of the program that produced this EDIF
file.
</output>
Solution 1:
One cause of this is tapping bits off a bus (with SLICE),
and "renaming" those nets to other netnames. "Renaming" nets
tapped off a bus bus means naming a bus bit using any
deviation from the "busname<bit_number>" convention.
Renaming nets is notlegal with HDL Direct methodology.
For instance, if you have an 8 bit bus "mybus<7..0>", and you
wish to tap bit 5 off, then the net that comes from the SLICE
or TAP must be either unnamed, or labelled as "mybus<5>".
Naming the net "mybus5" would be incorrect without inserting a BUFF
component (buffer) in between this net and the bus or SLICE.
To rename a net that has been sliced/tapped off a bus, you
may run the net to a BUFF, and then rename the output of the
BUFF to a new netname.
Consult Cadence's OpenBook and also Xilinx's Cadence
Interface/Tutorial Guide for more information on HDL Direct
naming methodology.
End of Record #2268 - Last Modified: 03/02/99 17:08 |
