Answers Database
FPGA Express v1.1: Does not allow Verilog parameters used as indices for arrays
Record #2270
Product Family: Software
Product Line: FPGA Implementation
Product Part: dc2ncf
Product Version: 1.3
Problem Title:
FPGA Express v1.1: Does not allow Verilog parameters used as indices for arrays
Problem Description:
Urgency: Standard
general description:
A legitimate syntax for Verilog is to assign a parameter to an indexed array
in the following manner:
parameter indexname;
.
.
.
assign a=b[indexname] ;
where 'indexname' is defined as a parameter.
This is currently not supported by FPGA Express v1.1
Solution 1:
Replace the paramter in the array index with the actual value. So, in the
example above, if indexname had been set to '3', then the assign statement
would become:
assign a = b[3];
Solution 2:
If replacing the parameter with the actual value is not convienent,
then logically 'AND' with '1' the expression with the paramter. In the
example above:
assign a = b[indexname];
would become:
assign a = b[indexname] & 1'b1;
End of Record #2270 - Last Modified: 11/11/97 12:34 |
