Answers Database M1.3/M1.4 Map: Map fails to pack RLOC'd carry logic in RPMs (Relationally Placed Macros) with LOC'd DFFs. Record #2280 Product Family: Software Product Line: FPGA Implementation Product Part: map Product Version: 1.4. Problem Title: M1.3/M1.4 Map: Map fails to pack RLOC'd carry logic in RPMs (Relationally Placed Macros) with LOC'd DFFs. Problem Description: Urgency: standard General Description: Map fails to pack RLOC'd carry logic (carry logic constrained using RLOC constraints) and LOC'd DFFs into the same COMPs (CLBs or IOBs). Valid constraints in the .UCF may direct both carry logic and DFFs into the same locations, but MAP does not merge them. Typically the RLOC'd carry logic is part of an RPM (Relationally Placed Macro). The RPM may or may not have an RLOC_ORIGIN property attached to it by the user. Solution 1: This problem may be seen when converting a floorplanned XACTstep 5.2.x/6.x design to M1. Map is not capable of packing logic with valid, overlapping RLOCs and LOCs together, resulting in the error described above. WORKAROUND for designs where the carry logic RPM has an RLOC_ORIGIN attached to it by the user: ------------------------------------------------------------ When converting these designs from XACT to M1, CSTCONV can be used to translate RLOC origins into hard LOC (location) constraints within the output .XTF file. The new .xtf and .ucf files produced by CSTCONV can then be used in the M1 flow. NOTE: To perform this translation, CSTCONV requires both a source .XTF and .CST file (XACT constraints file) for the design. Reference #: 10571 End of Record #2280 - Last Modified: 04/30/99 17:14

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