Answers Database
FPGA Express: Individual bits of a bus cannot be used as clock signals
Record #2282
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 3.1
Problem Title:
FPGA Express: Individual bits of a bus cannot be used as clock signals
Problem Description:
Urgency: Standard
General Description:
FPGA Express does not allow individual bits of a bus to be used as clock signals.
The following code will cause FPGA Express to crash:
library IEEE;
use IEEE.std_logic_1164.all;
entity busclk is
port (bigclk : in std_logic_vector(3 downto 0);
DIN : in std_logic_vector(3 downto 0);
RST, EN : in std_logic;
DOUT : out std_logic_vector(3 downto 0));
end busclk;
architecture busclk_arch of busclk is
begin
process( RST, bigclk(3), EN)begin
if( RST = '1' ) then
DOUT(3) <= '0';
elsif( bigclk(3)' event and bigclk(3) = '1' )then
if( EN = '1' )then
DOUT(3) <= DIN(3);
end if;
end if;
end process;
...
end busclk_arch;
Solution 1:
The workaround is to assign the bus bit to an intermediate signal first, as shown:
library IEEE;
use IEEE.std_logic_1164.all;
entity busclk is
port (bigclk : in std_logic_vector(3 downto 0);
DIN : in std_logic_vector(3 downto 0);
RST, EN : in std_logic;
DOUT : out std_logic_vector(3 downto 0));
end busclk;
architecture busclk_arch of busclk is
signal intclk3: std_logic;
begin
intclk3 <= bigclk(3);
process( RST, intclk3, EN)begin
if( RST = '1' ) then
DOUT(3) <= '0';
elsif( intclk3' event and intclk3 = '1' )then
if( EN = '1' )then
DOUT(3) <= DIN(3);
end if;
end if;
end process;
...
end busclk_arch;
End of Record #2282 - Last Modified: 09/10/99 11:28 |
