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SYNPLIFY: How to lock down I/O pins in HDL (Verilog/VHDL)?
Record #2379
Problem Title:
SYNPLIFY: How to lock down I/O pins in HDL (Verilog/VHDL)?
Problem Description:
Urgency: Standard
General Description: How to lock down I/O pins in the HDL using
Synplicity's synplify?
Solution 1:
Solution 2:
SDC
---
# Vendor specific constraints are passed in an .sdc file
define_attribute CLK xc_loc "P13"
define_attribute {A[3:0]} xc_loc "P19,P20,P23,P24"
define_attribute {B[3:0]} xc_loc "P25,P26,P27,P28"
define_attribute {O[3:0]} xc_loc "P48,P49,P50,P51"
Solution 3:
// Assigning I/O locations into HDL
// Verilog code
module iob_loc_ex (CLK, A, B, O);
input CLK /* synthesis xc_loc="P13" */;
input [3:0] A /* synthesis xc_loc="P19,P20,P23,P24" */;
input [3:0] B /* synthesis xc_loc="P25,P26,P27,P28" */;
output [3:0] O /* synthesis xc_loc="P48,P49,P50,P51" */;
reg [3:0] Q;
always @ (posedge CLK)
begin
Q <= A;
end
// token logic
assign O = Q & B;
endmodule
Solution 4:
-- Assigning I/O locations into HDL
-- VHDL code
library IEEE;
use IEEE.std_logic_1164.all;
entity iob_loc_ex is
port (CLK : in STD_LOGIC;
A, B : in STD_LOGIC_VECTOR (3 downto 0);
O : out STD_LOGIC_VECTOR (3 downto 0));
attribute xc_loc : string;
attribute xc_loc of CLK : signal is "P13";
attribute xc_loc of A : signal is "P19,P20,P23,P24";
attribute xc_loc of B : signal is "P25,P26,P27,P28";
attribute xc_loc of O : signal is "P48,P49,P50,P51";
end iob_loc_ex;
architecture xilinx of iob_loc_ex is
signal Q : STD_LOGIC_VECTOR (3 downto 0);
begin
U0: process (CLK)
begin
if (CLK'event and CLK='1') then
Q <= A;
end if;
end process;
-- Insert user's application here
O <= Q and B;
end xilinx;
End of Record #2379 - Last Modified: 05/19/99 11:35 |
