Answers Database
COREGEN: Latency of the Variable Multiplier core
Record #2411
Product Family: Software
Product Line: LogiCore
Product Part: Coregen IP Modules
Problem Title:
COREGEN: Latency of the Variable Multiplier core
Problem Description:
Urgency: standard
General Description:
The variable multiplier is pipelined several times in order to
enable it to run at high frequencies. The latency that
results from pipelining is a function of the width of the B
input.
Solution 1:
The Data is buffered on the input and output of the multiplier
cores. The total latency (number of clocks required to get the
first output) is a function of the width of the B variable
only.
Width of B input data Latency (# of clocks)
6 to 8 bits 4 clocks
9 to 16 bits 5 clocks
17 to 32 bits 6 clocks
End of Record #2411 - Last Modified: 03/02/99 18:04 | 
