Answers Database
HITOP M1.2.11: nd7331 - Input 'sclk_int' assigned to FCLK1 is used in logic.
Record #2462
Product Family: Software
Product Line: CPLD Implementation
Product Part: hitop
Product Version: 1.2
Problem Title:
HITOP M1.2.11: nd7331 - Input 'sclk_int' assigned to FCLK1 is used in logic.
Problem Description:
Urgency: Standard
General Description:
nd7331 - Input 'sclk_int' assigned to FCLK1 is used in logic. FCLK1 can only be used to fast clock m
acrocell registers and/or input pad registers.
ERROR:hi301 - Cannot fit the design into any of the specified devices. You may want to decrease the
pterm limit for a denser fit, or split thedesign into sub-designs, or try a larger device.
This message may occur if every IO is constrained in a ucf file, and the signal in question is broug
ht in through an IBUF eventhough it does not drive standard logic elements as suggested in the error
message.
Solution 1:
Remove the constraint from the clock input.
The 7300 architecture only has two pins for FCLKs. If one of them is constrained already, then the
other is implied.
Solution 2:
Replace the IBUF with a BUFG.
End of Record #2462 - Last Modified: 06/20/97 13:34 |
