Answers Database
SYNOPSYS FPGA/Design Compiler: How to constrain I/O pins in Synopsys designs (I/O pin locking)
Record #2500
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Compiler
Problem Title:
SYNOPSYS FPGA/Design Compiler: How to constrain I/O pins in Synopsys designs (I/O pin
locking)
Problem Description:
Urgency: Standard
General Description:
The question often arises as to how you can constrain your
I/O to specific pad locations in a Synopsys synthesis flow.
There is actually no support for adding attributes directly
to components in a VHDL or Verilog netlist, however, I/O location constraints can be added using one
of the following techniques
instead:
- adding constraints from a Synopsys compile script
- adding constraints to a .ucf file (for M1) constraint
- adding constraints to a .cst file (for XACT)
- adding constraints via the Xilinx Constraints Editor (A1.5 and later)
Solution 1:
From you Synopsys compile script, you may use the following command
before writing out the implementation netlist:
set_attribute <port_name> "pad_location" -type string "<pin_number>"
This is detailed in the XSI User/Interface guide, pg5-15.
You may also use a .cst file (for XACT) or a .ucf file (for M1)
constraint instead. Details on the syntax for these may be found
in the Xilinx Libraries Guide for the repective tool.
Solution 2:
There is actually no support for adding attributes directly
to components in a Verilog netlist, however, I/O location constraints can be added using one of the
following techniques
instead:
- adding constraints to a .cst file (for XACT)
- adding constraints to a .ucf file (for M1) constraint
End of Record #2500 - Last Modified: 08/12/98 14:56 |
