Answers Database
SYNPLIFY: How to infer Virtex Block SelectRAM+ using the syn_ramstyle attribute?
Record #2508
Product Family: Software
Product Line: Synplicity
Product Part: Synplify
Product Version: 5.0
Problem Title:
SYNPLIFY: How to infer Virtex Block SelectRAM+ using the syn_ramstyle attribute?
Problem Description:
Urgency: Standard
General Description:
Designers can enable the usage of Block selectRAMs by setting
the attribute syn_ramstyle to "block_ram".
Place the attribute on the output signal driven by the inferred RAM.
Remember to include the range of the output signal (bus) as part of
the name. For example,
define_attribute {a|dout[3:0]} syn_ramstyle "block_ram"
In HDL Analyst, the output signal name (in the example, "a" is the
instance name and "dout [3:0]" is the output signal name) will
become the instance name of the RAM.
Synplify generates a warning message when inferring these RAMs.
The message gives information about the RAM instance and
contains the phrase, "Removing sequential instance
<instance_name> view:<view_name> because there are no
references to its outputs." You can safely ignore this warning.
The following are limitations of inferring Block selectRAMs:
* ENA/ENB pins currently inaccessible [always tied to "1"]
* RSTA/RSTB pins currently inaccessible [always inactive]
* Automatic inference not yet supported, syn_ramstyle attribute
required for inferring Block RAMs
* Initialization of RAMs not supported
* Dual port with Read-Write on a port not supported
The designer has the option of instantiating the RAMB** cells
to which these limitations are overcomed. Please see
(Xilinx Solution 2022)
Solution 1:
-- VHDL example
-- Tested in Synplify 5.2.2a
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_example1 is
generic(data_width: integer:= 8;
address_width:integer := 8;
mem_depth: integer:= 256);
port (data: in std_logic_vector(data_width-1 downto 0);
address: in std_logic_vector(address_width-1 downto 0);
we, clk: in std_logic;
q: out std_logic_vector(data_width-1 downto 0));
end ram_example1;
architecture rtl of ram_example1 is
type mem_array is array (mem_depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
signal mem: mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of mem : signal is "block_ram";
signal raddress : std_logic_vector(address_width-1 downto 0);
begin
l0: process (clk)
begin
if (clk = '1' and clk'event) then
raddress <= address;
if (we = '1') then
mem(CONV_INTEGER(address)) <= data;
end if;
end if;
end process;
q <= mem(CONV_INTEGER(raddress));
end rtl;
Solution 2:
//Verilog example
//Tested in 5.2.2a.
module sp_ram(din, addr, we, clk, dout);
parameter data_width=16, address_width=10,mem_elements=600;
input [data_width-1:0] din;
input [address_width-1:0] addr;
input we, clk;
output [data_width-1:0] dout;
reg [data_width-1:0] mem[mem_elements-1:0] /*synthesis syn_ramstyle = "block_ram" */;
reg [address_width - 1:0] addr_reg;
always @(posedge clk)
begin
addr_reg <= addr;
if (we)
mem[addr] <= din;
end
assign dout = mem[addr_reg];
endmodule
Solution 3:
# SDC (Synplicity Design Constraint) example
# Tested in 5.2.2a
define_attribute {mem[<data_width-1>:0]} syn_ramstyle {block_ram}
# where mem is a two dimentional array ( memory_depth x data_width).
# <data_width-1> should be replaced by an integer value.
End of Record #2508 - Last Modified: 11/08/99 14:47 |
