Answers Database
NGD2VER: How are escaped names handled using the -ne option?
Record #2533
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngd2ver
Product Version: 2.1i
Problem Title:
NGD2VER: How are escaped names handled using the -ne option?
Problem Description:
Urgency: Standard
General Description:
The backslash is used as an escape character in Verilog.
In the Xilinx Alliance release, NGD2VER "escapes" any net
or block name containing illegal Verilog characters.
An escaped Verilog name can be recognized by a backslash
("\") prefix in front of that name, and a terminating blank space.
For example, the original net name "p1$i40/empty" becomes
"\p1$i40/empty " (note the terminating blank space). Because
of the Verilog illegal character "/" which is used as a hierarchy
designator in the input design.
The Verilog-legal set of characters is limited to the following:
a-Z, A-Z, 0-9, _, $ Please see (Xilinx solution 1535)
NGD2VER will also escape any reserved Verilog names that are
used in a design (e.g., "input", "output", etc.).
By rights, any OVI/IEEE 1364-compliant simulator *should* accept
escaped Verilog names.
Solution 1:
The -ne option (Do not escape names) will replace all invalid
Verilog characters (including "/") with the underscore ("_")
and not to escape the name with the backslash. For example,
without -ne:
wire \d_in3/INBLOCK/I ;
with -ne:
wire d_in3_INBLOCK_I;
End of Record #2533 - Last Modified: 11/17/99 11:36 |
