Answers Database M1.2/M1.3/M1.4 PAR (MAP): CLB Pin locking is not supported Record #2569 Product Family: Software Product Line: FPGA Implementation Product Part: par Product Version: 1.4. Problem Title: M1.2/M1.3/M1.4 PAR (MAP): CLB Pin locking is not supported Problem Description: Urgency: standard General Description: In the M1.2 and M1.3 releases of PAR, you cannot lock signals to specific CLB pins. This ability was formerly supported in the pre-M1 XACT software. This capability is not supported in the M1 software. In the M1 release, PAR may swap signals within the same CLB wherever it deems this is necessary. Lack of support for CLB pin locking also means that .FFX and .FFY constraints (locking down a flipflop to a particular CLB flipflop) will not work either, since such constraints would constrain the associated flipflop output pin to particular pins on the CLB. PAR will ignore these constraints if it thinks it can do a better job. Similarly, .F and .G constraints constraining combinational logic to either an F or G function generator also will be ignored by PAR, since constraining a signal to a particular function generator also implies you are constraining it to a particular set of pins. Solution 1: The workaround if a specific configuration of a CLB or set of macro CLBs is required is to implement the configuration in the EPIC Design Editor and generate a physical macro out of the configured CLB. You must then generate a symbol for this macro and instantiate it in your design. End of Record #2569 - Last Modified: 01/12/98 14:35

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!