Answers Database M1 LOGIBLOX/XBLOX: Naming of RAM Address and Data pins differs in LogiBLOX And X-BLOX Record #2631 Product Family: Software Product Line: FPGA Implementation Product Part: logiblox Problem Title: M1 LOGIBLOX/XBLOX: Naming of RAM Address and Data pins differs in LogiBLOX And X-BLOX Problem Description: Urgency: standard General Description: Logiblox names RAM Data and Address pins differently from the way X-BLOX did. DATA pins: XBLOX names Data pins as "D_IN"<index>, Logiblox names them as "D"<index>. ADDRESS pins: XBLOX names Address pins as "ADDR"<index>, Logiblox names them as "A"<index> Solution 1: LogiBLOX modules are designed to be compatible with the Xilinx Unified Library standard, and as a result the pin naming on LogiBLOX RAM modules is consistent with Xilinx Unified Library conventions. This makes it easy to replace Xilinx library RAM macros with LogiBLOX modules in HDL designs. However, because these conventions differ from the naming conventions used in X-BLOX RAM modules, conversion of designs containing X-BLOX RAMs to M1 requires modification of all the port references in the former X-BLOX RAM instantiations. End of Record #2631 - Last Modified: 06/23/98 11:01

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