Answers Database
M1, ViewSynthesis: Analyzing Simprims and Unified libraries with SpeedWave
Record #2687
Product Family: Software
Product Line: ViewLogic
Product Part: Viewsynthesis
Product Version: 7.2
Problem Title:
M1, ViewSynthesis: Analyzing Simprims and Unified libraries with SpeedWave
Problem Description:
Urgency: Standard
Although the Simprims and Unified library VHDL source files are VITAL
compliant, the SpeedWave analyzer in WorkView Office 7.31 is unable to
analyze them due to an internal limitation on the number of terms in an
expression. According to ViewLogic SPR 22362, the failure occurs when a
single expression has more than 24 terms.
The SpeedWave analyzer translates VHDL source into C code, which is compiled
by the Microsoft C compiler. For the 32- and 64-input gates found in the
VITAL VHDL source files, the SpeedWave analyzer creates expressions that are
too complex for the Microsoft compiler, which fails with the error:
.../vantage.c (1980): fatal error C1013: compiler limit: too many
open parentheses
Solution 1:
This limitation can be worked around using parentheses to create
sub-expressions of fewer than 24 terms each.
The VHDL source files have been modified with sub-expressions of fewer than
24 terms each. Because Xilinx SQA has not yet qualified these modified
libraries, there are only available from ViewLogic. The modified VHD file is
available here:
ftp://ftp.viewlogic.com/pub/support/pc/Workview_Office/AppNotes
The file is called simprim_VITAL.vhd
End of Record #2687 - Last Modified: 10/14/97 14:04 |
