Answers Database
1.5i MAP ERROR:basnu - logical block "core/data" of type "INC_DEC_TWO_COMP_6" is unexpanded.
Record #2700
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.3.
Problem Title:
1.5i MAP ERROR:basnu - logical block "core/data" of type "INC_DEC_TWO_COMP_6" is unexpanded.
Problem Description:
Urgency: HOT
Problem Description:
A design compiled with Design Compiler may get a warning
about an unexpanded block from ngdbuild, followed by
an error from map on the same unexpanded block. This
unexpanded block may be DesignWare component that
does exist in the xdw_xcXXXX.sldb file, like an
INC_DEC_TWO_COMP_6, ADD_SUB_UB_12, etc.
Solution 1:
Resolution 1:
Add following synthesis attributes into .synopsys_dc.setup file.
Or use Xilinx template for .synopsyy_dc.setup at
$XILINX/synopsys/examples/template.synopsys_dc.setup_dc.
Refer to Synopsys IVIEW on-line docuementation for more
information on the following attributes.
edifout_netlist_only = true
edifout_no_array = true
Solution 2:
Your .synopsys_dc.setup file may be missing some of the
required EDIF writer settings. Use the template.synopsys_dc.setup_dc
file as a reference for your .synopsys_dc.setup file.
The template.synopsys_dc.setup_dc can be found in
$XILINX/synopsys/examples
End of Record #2700 - Last Modified: 04/12/99 17:32 |
