Xilinx Answer #2713 : SYNPLIFY: How to instantiate a pre-optimized (black-box) netlist (XNF, EDIF, NGC, COREGEN, LOGIBLOX) file in HDL (Verilog/VHDL)?

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SYNPLIFY: How to instantiate a pre-optimized (black-box) netlist (XNF, EDIF, NGC, COREGEN, LOGIBLOX) file in HDL (Verilog/VHDL)?

Record #2713
Product Family: Software

Product Line: Synplicity

Product Part: Synplify

Problem Title:
SYNPLIFY: How to instantiate a pre-optimized (black-box) netlist (XNF, EDIF, NGC, COREGEN, LOGIBLOX) file in HDL (Verilog/VHDL)?

Problem Description:
Urgency: Standard

General Description: How to instantiate a pre-optimized
netlist (XNF, EDIF, NGC, CoreGen, LogiBlox) file in the
Synplify HDL flow?

Use the black_box attribute to specify that an instantiated
component is a black box (that only its interface is defined
for synthesis).

When to use black boxes:

o Xilinx primitive instantiation

o User-designed macros whose functionality is defined in a
   schematic editor, or another input source.

Note: The bus-notation used in the Synplify netlist and the
pre-optimized netlist must match. Please see
(Xilinx Solution 4272) for more information. The EDIF format
generated in Synplify 5.x differs in bus notation from the XNF
output file previously generated in versions 3.0 and below.

+------+------+------+------------------------------+ | Ver. | 3.x | 5.x | Comments | +------+------+------+------------------------------+ | XNF | B | B | Buss signals expanded | +------+------+------+------------------------------+

| EDIF | X | B(I) | Not using "syn_noarrayports" | +------+------+------+------------------------------+ | EDIF | X | B[I] | Using "syn_noarrayports" | +------+------+------+------------------------------+

Solution 1:

// Verilog black box example

module tenths_ex (clkint, clkenable, xcountout);
input clkint, clkenable;
output [9:0] xcountout;

tenths XCOUNTER (.CLOCK (clkint), .CLK_EN (clkenable),
            .Q_OUT (xcountout));

endmodule

module tenths (CLOCK, CLK_EN, Q_OUT) /* synthesis black_box */;
input CLOCK, CLK_EN;
output [9:0] Q_OUT;

endmodule

Solution 2:

-- VHDL black box example

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity tenths_ex is
     port ( clkint, clkenable : in STD_LOGIC;
         xcountout : out STD_LOGIC_VECTOR(9 downto 0));
end tenths_ex;

architecture xilinx of tenths_ex is

attribute black_box : boolean;

component tenths port ( CLOCK : in STD_LOGIC; CLK_EN : in STD_LOGIC; Q_OUT : out STD_LOGIC_VECTOR(9 downto 0)); end component; attribute black_box of tenths : component is true;

begin

XCOUNTER : tenths port map( CLOCK => clkint,
                    CLK_EN => clkenable,
                    Q_OUT => xcountout
                  );

end xilinx;

End of Record #2713 - Last Modified: 06/14/99 16:05

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