Answers Database
M1.5 PAR/EPIC: Both say that BEL doesn't exist in the NCD, but it does.
Record #2777
Product Family: Software
Product Line: FPGA Implementation
Product Part: Epic
Problem Title:
M1.5 PAR/EPIC: Both say that BEL doesn't exist in the NCD, but it does.
Problem Description:
Urgency: Standard
General Description:
PAR and EPIC both say that a BEL doesn't exist in the NCD, but it does. The PCF file contains a TIME
GRP that contains the BEL. When the NCD and PCF files are loaded into either PAR or EPIC, they issu
e warnings that the BEL was not found. But visual inspection through EPIC confirms that the BEL exi
st.
Solution 1:
The problem is this: when the mapper creates comps it will fill them with the appropriate BELs. Wit
h these bels you can attach timing constraints.
The problem arises when you run the Logic Block Editor in EPIC and modify a comp that contains bels.
Since a user cannot guarantee that they'll always create a valid COMP, as far as connectivity and
programming, when they exit LBE then the COMP will be turned into what is known as a 'SuperBel' wher
e the system treats the entire COMP as a BEL. Hence any BELs internal to that comp will be oblitera
ted thus rendering any timing constraints, which reference those BELs, useless.
This is a known problem. The only workaround is not to modify CLB's, IOB's, or other COMPs that are
pointed to by a time group or a timing constraint.
End of Record #2777 - Last Modified: 05/26/99 07:23 |
