Answers Database
M1.3.7, M1.4.12 LOGIBLOX: rloc_orgin properties attached to Logiblox ADD/SUB modules are ignored by place and route tools.
Record #2782
Product Family: Software
Product Line: FPGA Implementation
Product Part: logiblox
Product Version: 1.3
Problem Title:
M1.3.7, M1.4.12 LOGIBLOX: rloc_orgin properties attached to Logiblox ADD/SUB modules are
ignored by place and route tools.
Problem Description:
URGENCY: Standard
GENERAL DESCRIPTION
The rloc_orgin attribute assigned to adders or subtractors created by LogiBLOX are ignored by the M1
place and
route tools.
The reason for this is that LogiBLOX does not create RPMs
when it generates Adder and Subtractor modules in the M1.3
and M1.4 releases. In these two releases, RLOCs are only used
to constrain logic into CLBs with carry logic. There are no
H_SET constraints generated to group the CLBs into RPMs
(Relationally Placed Macros). Since the modules are not
RPM'ed, RLOC_ORIGIN properties attached to these modules do
not work.
The M1 tools ignore the RLOC_ORIGIN constraint
without giving any warning or error messages.
You can verify that this is the case by viewing the placement
of the placed and routed design in the EPIC editor.
In the M1.5 release, Adders and Subtractors have been RPM'ed
(H_SET properties have been added to the modules) to correct
this problem.
Reference #: 102618
Solution 1:
The preferred solution is to regenerate the adder or
subtractor using the M1.5 version of LogiBLOX, as this
version of LogiBLOX will generate RPM's for types of modules.
Solution 2:
One workaround for this problem is to manually add
RLOC constraints to all the CLBs making up the adder or
subtractor, as well as attaching the same H_SET attribute
to them. This can be done in the .PCF physical constraints
file.
The CLB names are for all the components in a given
adder/subtractor can be determined by looking for all
component units having the same prefix in their names.
End of Record #2782 - Last Modified: 09/02/98 19:39 |
