Answers Database M1.3.7 TRCE - Timing constraint does not relax period constraint Record #2828 Product Family: Software Product Line: FPGA Implementation Product Part: trce Product Version: 1.3 Problem Title: M1.3.7 TRCE - Timing constraint does not relax period constraint Problem Description: Timing constraint does not relax period constraint: TS20 = MAXDELAY FROM TIMEGRP "wr_add" TO TIMEGRP "freeq_counter" 60 nS ; Reference # 100196 Solution 1: A patch is available at: ftp://ftp.xilinx.com/pub/swhelp/M1.3_alliance/trce_sun091597.tar.Z ftp://ftp.xilinx.com/pub/swhelp/M1.3_alliance/trce_sol091597.tar.Z ftp://ftp.xilinx.com/pub/swhelp/M1.3_alliance/trce_hp091597.tar.Z ftp://ftp.xilinx.com/pub/swhelp/M1.3_alliance/trce_nt.zip This patch is also available from the M1.3 Performance Pack CD. End of Record #2828 - Last Modified: 11/20/98 16:42

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