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SYNPLIFY: How to force an IOB NODELAY latch or flip-flop in HDL (Verilog/VHDL)?
Record #2831
Problem Title:
SYNPLIFY: How to force an IOB NODELAY latch or flip-flop in HDL (Verilog/VHDL)?
Problem Description:
Urgency: Standard
General Description:
XC4000e/ex/xl IOB flip-flops and latches have a delay block between
the external pin and the D input. The xc5200 IOB, also, provides a
programmable delay element to control input set-up time. This delay
prevents any possible hold-time violations if you have a clock signal
that is also coming into the device and clocking the input flip-flop
or latch. You can remove this delay with the NODELAY attribute. The
NODELAY attribute decreases the setup-time requirements and introduces
a small hold-time.
Solution 1:
-- XC4000e/ex/xl and xc5200 -- VHDL code
-- Passing NODELAY through a constraints file (.sdc)
library IEEE;
use IEEE.std_logic_1164.all;
entity ifd_ex is
port (CLK, A, B: in STD_LOGIC;
O: out STD_LOGIC);
end ifd_ex;
architecture xilinx of ifd_ex is
signal Q : STD_LOGIC;
begin
U0: process (CLK)
begin
if (CLK'event and CLK='1') then
Q <= A;
end if;
end process;
-- token logic
O <= Q and B;
end xilinx;
# Vendor specific constraints are passed in an .sdc file
define_attribute A xc_nodelay 1
Solution 2:
For xc4000e/ex/xl, you can remove the default delay by instantiating
a flip-flop or latch with a NODELAY attribute. Input flip-flops or
latches with an _F suffix have a NODELAY attribute assigned to the
cell. For example, the components IFD_F or ILD_1F remove this delay
because these cells include a NODELAY attribute.
*******************************************
NOTE: instantiating IFD_F in VHDL currently(v5.3.1 and earlier) result in IFD with incorrect
FAST attribute. Synplicity is aware of this. The workaround is to instantiate IFDX and pass
NODELAY attribute as follows:
attribute NODELAY: string;
attribute nodelay of <instance name> label is "TRUE";
*******************************************
However, since the xc5200 IOB does not include flip-flops or latches.
The xc5200 family provides direct connections from each IOB to the
registers in the adjacent CLB in order to emulate IOB registers.
The designer has the option of passing the "xc_nodelay" attribute
through a constraints file (.sdc) or the HDL code.
# Vendor specific constraints are passed in an .sdc file
define_attribute {<input_port_name>} xc_nodelay 1
Solution 3:
// XC4000e/ex/xl only -- Verilog code
// Instantiate an IFD_F
`include "/products/synplify/lib/xilinx/xc4000.v"
module ifd_ex (CLK, A, B, O);
input A ;
input B, CLK;
output O;
wire Q;
IFD_F U0 (.Q (Q), .D (A), .C (CLK));
// token logic
assign O = Q & B;
endmodule
Solution 4:
// XC4000e/ex/xl and xc5200 -- Verilog code
// Passing NODELAY through HDL
module ifd_ex (CLK, A, B, O);
input A /* synthesis xc_nodelay=1 */;
input B, CLK;
output O;
reg Q;
always @(posedge CLK)
Q <= A;
// token logic
assign O = Q & B;
endmodule
Solution 5:
// XC4000e/ex/xl and xc5200 -- Verilog code
// Passing NODELAY through a contraints file (.sdc)
module ifd_ex (CLK, A, B, O);
input A;
input B, CLK;
output O;
reg Q;
always @ (posedge CLK)
begin
Q <= A;
end
// token logic
assign O = Q & B;
endmodule
# Vendor specific constraints are passed in an .sdc file
define_attribute A xc_nodelay 1
Solution 6:
-- XC4000e/ex/xl only -- VHDL code
-- Instantiate an IFD_F
library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;
entity ifd_ex is
port (CLK, A, B : in STD_LOGIC;
O : out STD_LOGIC);
end ifd_ex;
architecture xilinx of ifd_ex is
signal Q : STD_LOGIC;
begin
U0 : IFD_F port map (Q => Q,
D => A,
C => CLK);
-- token logic
O <= Q and B;
end xilinx;
Solution 7:
-- XC4000e/ex/xl and xc5200 -- VHDL code
-- Passing NODELAY through HDL
library IEEE;
use IEEE.std_logic_1164.all;
entity ifd_ex is
port (CLK, A, B: in STD_LOGIC;
O: out STD_LOGIC);
attribute xc_nodelay : boolean;
attribute xc_nodelay of A : signal is true;
end ifd_ex;
architecture xilinx of ifd_ex is
signal Q : STD_LOGIC;
begin
U0: process (CLK)
begin
if (CLK'event and CLK='1') then
Q <= A;
end if;
end process;
-- token logic
O <= Q and B;
end xilinx;
End of Record #2831 - Last Modified: 02/01/00 17:28 |
