Answers Database


XABEL, Foundation F1.3: Internal Error 0001: assert event at line 274 in file Z:\fit\blif2net\TSOINTER.CXX


Record #2834

Product Family: Software

Product Line: Data I/O

Product Part: xabel

Problem Title:

XABEL, Foundation F1.3:	Internal Error 0001: assert event at line 274 in file
Z:\fit\blif2net\TSOINTER.CXX



Problem Description:
Urgency: Hot

General Description:

When synthesizing a CPLD ABEL design in Foundation F1.3, the
following error may occur:

Internal Error 0001: assert event at line 274 in file
Z:\fit\blif2net\TSOINTER.CXX


Solution 1:

If the patch does not fix the problem, another workaround is to
have XABEL write out a Plusasm (.PLD) file instead of and Edif
(.EDN) file. This PLD file will be read by the Design Manager
rather than the EDN file for implementation.

**This workaround only applies to top-level ABEL designs. This
workaround does not work for designs which have a top-level
schematic with lower-level ABEL modules.

To tell Foundation/XABEL to write out a .PLD file, a
modification must be made to the SUSIE.INI file:

* From Foundation Project Manager, select File->Configuration.
* Hit the "View Ini File" button.
* Locate the line which reads ";XABELNETLIST=PLUSASM" and
   remove the ; at the beginning of the line to "uncomment" it.

Note that you may see an Error at the end of Synthesis, saying
that Synthesis Failed. Assuming there are no "real" errors in
the code, this error may be caused by the fact that Foundation
expects to see an EDIF file (.EDN) at the end of the synthesis.
Since only a .PLD file was generated, it thinks synthesis
failed. You can check the log window in the Project Manager to
see if this was the problem. If you see a line stating:

"abl2pld has succeeded..."

then you should be fine. Most likely, you'll also see some
lines after this which state:

Hde: abl2edif.exe -failed
Hde: <design>.EDN was not created

However, since abl2pld was successful, you should have a .PLD
file, and be able to continue with the flow.

XABEL will synthesize the code to a PLD file, and the
PLD file will automatically be read by the Design Manager when
implementing the design.

For Functional Simulation, follow the following steps:

*Enter the Design Manager from the Project Manager.
*In Design Manager, select Design->New Version, then
    Design->New Revision.
*Go into the Flow Engine (Tools->Flow Engine)
*"Step" the flow, so that it goes only up through Translate.
*Go back to Foundation Project Manager, and choose
    Tools->Checkpoint Simulation...
*Choose the appropriate <device>.NGD file.
*The Simulator will load the netlist for Functional Simulation.



Solution 2:

A patch is available to fix this problem. It is available in
the File Download area of the Answers Page on the Xilinx Web
Site.

ftp://ftp.xilinx.com/pub/swhelp/foundation/xabelfix.zipInternet Link




End of Record #2834 - Last Modified: 03/03/99 10:48

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!