Answers Database
SYNPLIFY: How to force IOB flip-flops vs a CLB flip-flops using xc_ioff?
Record #2867
Product Family: Software
Product Line: Synplicity
Product Part: Synplify
Product Version: 5.0
Problem Title:
SYNPLIFY: How to force IOB flip-flops vs a CLB flip-flops using xc_ioff?
Problem Description:
Urgency: Standard
General Description:
How to force an IOB flip-flops vs a CLB flip-flops using xc_ioff?
A CLB flip-flop is a good candidate to get pushed into the IOB,
under the following circumstances outlined in
(Xilinx Solution 2207).
You may choose to allow the Xilinx Alliance software to merge
the flip-flops into the IOB with the "map -pr" option.
Solution 1:
SDC
---
You can specify to disable the pushing of flip-flops into the IOB
in SDC file.
define_attribute <port_name> xc_ioff 0
The default value is 1 (enable)
To globally disable the pushing of flip-flops into the IOB for the
entire design.
define_global_attribute xc_ioff 0
Solution 2:
Verilog
-----
module EXAMPLE (RST, CLK, ENB, A, B, Q_OUT);
input RST, CLK, ENB, A, B;
output Q_OUT /* synthesis xc_ioff = 0 */ ;
reg Q_OUT;
wire D_IN;
assign D_IN = A & B;
// Flip-flop with asynchronous reset and clock enable
always @(posedge RST or posedge CLK)
if (RST)
Q_OUT <= 1'b0;
else if (ENB)
Q_OUT <= D_IN;
endmodule
Solution 3:
VHDL
----
library IEEE, synplify;
use IEEE.std_logic_1164.all,
synplify.attributes.all;
entity EXAMPLE is
port (RST, CLK, ENB, A, B : in std_logic;
Q_OUT : out std_logic);
attribute xc_ioff of Q_OUT : signal is false;
end EXAMPLE;
architecture XILINX of EXAMPLE is
signal D_IN : std_logic;
begin
D_IN <= A and B;
-- Flip-flop with asynchronous reset and clock enable
process (ENB, RST, CLK)
begin
if (RST = '1') then
Q_OUT <= '0';
elsif rising_edge(CLK) then
if (ENB = '1') then
Q_OUT <= D_IN;
end if;
end if;
end process;
end XILINX;
End of Record #2867 - Last Modified: 01/13/00 16:42 |
