Answers Database


How to ignore/remove LOC constraints on PADS?


Record #2898

Product Family: Software

Product Line: FPGA Implementation

Product Part: par

Problem Title:
How to ignore/remove LOC constraints on PADS?


Problem Description:
Urgency: Standard

General Description:

LOC constraints defined in schematics are automatically passed to PAR by the
mapper, using the .pcf file.


Solution 1:

LOC constraints passed from the schematic can be modified or ignored
using the following options.

1. If ngdbuild is run with the "-r" switch, all location constraints
    will be ignored. When using DM/FE, this switch can be added to the
    flow by using the Template Manager to define a custom template.

2. The .pcf file can be modified with a text editor between mapping and PAR.

3. Location constraints can be modified by editing the design in EPIC. Select
    and attibute individual components to modify their constraints. EPIC will
    write the changes to the .pcf file when a save is performed.




End of Record #2898 - Last Modified: 12/12/97 16:38

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!