Answers Database
NGD2VER: How to simulate the XC3000 family simulation netlists?
Record #2931
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngd2ver
Product Version: 1.3.
Problem Title:
NGD2VER: How to simulate the XC3000 family simulation netlists?
Problem Description:
Urgency: Standard
General Description:
Verilog netlists generated by NGD2VER specify the
global reset signal as a Verilog port called "GR" at all
points of the flow for the XC3000A/L and XC3100A/L
architectures.
Solution 1:
The Global Reset (GR) signal in the XC3000A/L and XC3100A/L
architecture is modeled differently in functional simulation netlists
and SimPrims library-based netlists generated by NGD2VER. In the
Verilog Unified Library, GR is modeled as a wire within a global
module, while in a SimPrims-based netlist, it is always modeled as an
external port. As a result, you cannot use the same test bench file for
both Unified library simulation and SimPrims-based simulation.
End of Record #2931 - Last Modified: 06/22/99 10:37 |
