Answers Database
SYNPLIFY: How to use the syn_useenables attribute?
Record #2977
Product Family: Software
Product Line: Synplicity
Product Part: Synplify
Product Version: 5.0
Problem Title:
SYNPLIFY: How to use the syn_useenables attribute?
Problem Description:
Urgency: Standard
General Description:
How to use the syn_useenables attribute?
By default, Synplify the syn_useenables attribute is set to true.
This attribute is used to generate register components with clock
enable pins on them. If you do not want this, or the technology
you are using does no support it, then you can disable this behavior.
Solution 1:
Verilog
-------
module dff (d_in, clk, rst, ce, q_out);
input [7:0] d_in;
input clk, rst, ce;
output [7:0] q_out;
reg [7:0] q_out /* synthesis syn_useenables = 0 */;
always @(posedge clk or posedge rst)
if (rst)
q_out <= 8'h0;
else
if (ce)
q_out <= d_in;
endmodule
Solution 2:
Use the Attributes Pane of SCOPE and specify the syn_useenables attribute
with a value of 0 (disabled) for the registers you do not want to have enable
pins on.
End of Record #2977 - Last Modified: 05/13/99 14:24 |
