Xilinx Answer #3014 : M1.5i/2.1i: TRCE: "HIGH" or "LOW" keyword for PERIOD may not work as expected with OFFSET

Answers Database

M1.5i/2.1i: TRCE: "HIGH" or "LOW" keyword for PERIOD may not work as expected with OFFSET

Record #3014
Product Family: Software

Product Line: FPGA Implementation

Product Part: trce

Product Version: 1.3

Problem Title:
M1.5i/2.1i: TRCE: "HIGH" or "LOW" keyword for PERIOD may not work as expected with OFFSET

Problem Description:
Urgency: standard

General Description:

It may not be obvious that the HIGH and LOW qualifiers for the
PERIOD constraint define the length and polarity "first clock
pulse", not simply the duty cycle. This becomes relevant when
using the PERIOD in conjunction with the OFFSET constraint. For
example, as far as the duty cycle is concerned, the following
two PERIOD constraints are identical:

1) NET clock PERIOD = 30ns high 18; 2) NET clock PERIOD = 30ns low 12;

But if an OFFSET constraint is used, such as:

NET qoutpad OFFSET = OUT 20 AFTER clockpad;

then the two PERIOD constraints will yield different results in TRCE.

~~~~~~~~~~~~~~~~~~~~~~~~
For 1), this means the first clock pulse is high for 18ns,
followed by a low level for 12ns. Since it is implied there
will be an edge at time 0, the OFFSET constraint will
be calculated with that assumption.

==================================================================== Timing constraint: COMP "qoutpad" OFFSET = OUT 20.000 nS AFTER COMP "clockpad" ; 1 item analyzed, 0 timing errors detected. Minimum allowable offset is 16.587ns. -------------------------------------------------------------------- Slack: 3.413ns path clockpad to qout relative to 12.627ns delay constraint qout to qoutpad and 20.000ns offset clockpad to qoutpad

~~~~~~~~~~~~~~~~~~~~~~~
For 2), this means the clock is low for 12ns initially,
followed by a 18ns high. In this case, the OFFSET constraint
will now be calculated assuming the edge will come at
time=12ns. 12ns will be subtracted from the allowable offset
(20ns).

====================================================================
Timing constraint: COMP "qoutpad" OFFSET = OUT 20.000 nS AFTER COMP "clockpad" ;
1 item analyzed, 1 timing error detected.
Minimum allowable offset is 28.587ns.
--------------------------------------------------------------------
Slack: -8.587ns path clockpad to qout relative to
12.627ns delay constraint qout to qoutpad and
8.000ns offset clockpad to qoutpad

Notice the "8.000ns" on the last line; this is 20.000ns-12ns.
The "Minimum allowable offset" is now 12ns more than 1);
28.587ns = 16.587ns + 12ns.

There is also the case with OFFSET IN BEFORE/AFTER. This will result in addition instead of subtract ion of the offset clock to flop delay. Therefore you would have 20.000ns+12.000ns=32.000ns.

Solution 1:

The resolution to this issue is never use the LOW qualifier when using offset. Always use the HIGH q ualifier to specify the duty cycle.

End of Record #3014 - Last Modified: 07/13/99 16:00

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!