Answers Database


M1.3 Translate: OPTX error:x4kdr: 7 ---netcheck: Macros instantiated in ABEL.


Record #3064

Product Family: Software

Product Line: FPGA Implementation

Product Part: map

Product Version: 1.3

Problem Title:
M1.3 Translate: OPTX error:x4kdr: 7 ---netcheck: Macros instantiated in ABEL.


Problem Description:
Keyword: M1.3, ABEL, OPTX, x4kdr.

Urgency: Hot

The design can not pass the translate stage due to the OPTX error. The error message is as follow: E
RROR: x4kdr: 7 - Netcheck: More than one active source pin was found for signal <signal_name>. Pleas
e check to ensure that all signals only have one driver...


Solution 1:

Workaround:
This problem may happen if you are using foundation F1.3 and have ABEL macros instantiated in the sc
hematic. The solution to that is resumed in the following steps: Under Design click on IMPLEMENT--->
Click on OPTION--->Click on EDIT TEMPLATE--->Under OPTIMIZATION select SPEED or AREA, then click on
OK and reimplement.
If the instantiated macros were written in VHDL, please look at solution record 2993.




End of Record #3064 - Last Modified: 12/12/97 14:49

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!