Answers Database
M1 LOGIBLOX: How to LOC or constrain a data register to a range of CLB's
Record #3072
Product Family: Software
Product Line: FPGA Implementation
Product Part: logiblox
Problem Title:
M1 LOGIBLOX: How to LOC or constrain a data register to a range of CLB's
Problem Description:
Urgency: Standard
General Description:
When attempting to constrain a LogiBlox-instantiated data
register module into a range of CLB's in a schematic capture
tool, the following constraint format does not work:
LOC=CLB_R1C1:CLB_R10C1
Solution 1:
Instead of constraining the registers by specifying constraints
in the schematic, you must LOC each individual flop via the UCF
file (User Constraints File). The flip-flops inside the
LogiBLOX modules are named FLOP0, FLOP1, FLOP2, and so on, so if you have a 20-bit data register, yo
u would reference them
as FLOP0 through FLOP19.
For example, if in Foundation, the instance name (as opposed to
the modulename) of the LogiBLOX module is L1, then the LOC
constraints can be specified as follows in the UCF, assuming
that L1 is a 20-bit data register:
INST L1/FLOP0 LOC=CLB_R1C1;
INST L1/FLOP1 LOC=CLB_R1C1;
INST L1/FLOP2 LOC=CLB_R2C1;
..
INST L1/FLOP19 LOC=CLB_R10C1;
End of Record #3072 - Last Modified: 12/08/98 19:52 |
