Answers Database
M1.5i/2.1i: TRCE: Path tracing behavior for RAMs
Record #3143
Product Family: Software
Product Line: FPGA Implementation
Product Part: trce
Problem Title:
M1.5i/2.1i: TRCE: Path tracing behavior for RAMs
Problem Description:
Urgency: Standard
General Description:
The following will describe what paths TRACE (and Timing Analyzer) will
control in regards to RAMs.
Solution 1:
For Asynchronous RAMs
===========================
Paths that end at RAMs are traced, including the WE, D, and Address pins. TRCE
should determine the setup time.
Paths that start at RAMs are traced. TRCE determines the worst-case time from a
change on D or WE to data valid (and on to the destination).
Paths that propagate through RAMs are traced only if they arrive at the address
pins, but not if they arrive at the D or WE pins. A change on an address pin
propagate just as they do for ordinary LUTs. However, propagation of changes on D
or WE are assumed to be of interest only when the RAM is being read during a
write operation. If you want PAR to control the delay on paths through the D or WE
inputs, you must split the delay requirement into two segments: one ending at the
RAM input pin, and the other beginning at the RAM output.
Solution 2:
For Dual Port Synchronous RAMS
===============================
Paths that end at RAMs are traced, except for the paths that end at
the DPRA0 to DPRA3 pins. Read address inputs cannot impact paths
that end at a RAM (write function).
Paths that start at RAMs are traced. PAR determines the worst-case time
after WCLK transition to data valid.
Paths that propagate through RAMs are traced only if they arrive at
the address pins (A? to SPO paths and DPRA? to DPO paths), but not if
they arrive at the D or WE pins. A change on an address pin propagate
just as they do for ordinary LUTs. However, propagation of changes on
D or WE are assumed to be of interest only when the RAM is being read
during a write operation. If you want PAR to control the delay on paths
through the D or WE inputs, you must split the delay requirement into
two segments: one ending at the RAM input pin, and the other beginning
at the RAM output.
Solution 3:
For Single-Port Synchronous RAMs
================================
Paths that end at RAMs are traced, including the WE, D, and Address pins.
PAR determines the setup time with respect to the WCLK pin.
Paths that start at RAMs are traced. PAR determines the worst-case time
after WCLK transition to data valid.
Paths that propagate through RAMs are traced only if they arrive at
the address pins, but not if they arrive at the D or WE pins. A change
on an address pin propagate just as they do for ordinary LUTs. However,
propagation of changes on D or WE are assumed to be of interest only
when the RAM is being read during a write operation. If you want PAR
to control the delay on paths through the D or WE inputs, you must
split the delay requirement into two segments: one ending at the RAM
input pin, and the other beginning at the RAM output.
End of Record #3143 - Last Modified: 07/19/99 07:02 |
