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Foundation XVHDL, NGDBuild: Warning:basnu-The input pad net "<nonclk signal>" is driving one or more clock loads, but is not using a dedicated clock buffer
Record #3145
Product Family: Software
Product Line: Metamor
Product Part: Foundation XVHDL
Product Version: 3.02
Problem Title:
Foundation XVHDL, NGDBuild: Warning:basnu-The input pad net "<nonclk signal>" is driving one
or more clock loads, but is not using a dedicated clock buffer
Problem Description:
Urgency: Standard
General Description:
NGDBUILD may give the following warnings/error:
"WARNING:basnu - Multiple blocks named "view_1/<nonclk_port>"
in block "<vhdl file>".
WARNING:basnu - The input pad net "<nonclk_port>" is driving
one or more clock loads, but is not using a dedicated clock
buffer.
ERROR: basnu - logical net "<nonclk_port>" has both active and
tristate drivers"
or,
"ERROR: basnu - logical net "<nonclk_port>" has multiple
drivers"
when instantiating IBUFs and BUFGs with VHDL in Foundation.
Solution 1:
One cause of this problem is not using upper-case to declare the
component and the ports on the instantiated components.
IE:
component BUFGS
port(I:in bit;
O:out bit);
end component;
End of Record #3145 - Last Modified: 01/03/00 11:01 |
