Xilinx Answer #3234 : Foundation XVHDL: Using mode pins (MD0, MD1, MD2) for general I/O

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Foundation XVHDL: Using mode pins (MD0, MD1, MD2) for general I/O

Record #3234
Product Family: Software

Product Line: Metamor

Product Part: Foundation XVHDL

Product Version: 3.0.4

Problem Title:
Foundation XVHDL: Using mode pins (MD0, MD1, MD2) for general I/O

Problem Description:
Urgency: Standard

General Description:

The device configuration mode pins may be used as general I/O
after configuration by instantiating the special mode pin
components (MD0, MD1, MD2) in your VHDL code.

Solution 1:

library IEEE;
use IEEE.std_logic_1164.all;

entity mode is

port ( d : out std_logic);

end mode;

architecture mode_arch of mode is

component MD0
      port ( I : out std_logic); --used as input pin
end component;

component MD1 port ( O : in std_logic); --used as output pin end component;

component MD2
      port ( I : out std_logic); --used as input pin
end component;

component IBUF
      port ( I : in std_logic; O : out std_logic);
end component;

component OBUF
      port ( I : in std_logic; O : out std_logic);
end component;

signal a,b,c,abuf,bbuf,cbuf : std_logic;

begin

U1: MD0 port map ( I => abuf );
U2: IBUF port map ( I => abuf, O => a );
U3: MD2 port map ( I => bbuf );
U4: IBUF port map ( I => bbuf, O => b );
U5: MD1 port map ( O => cbuf );
U6: OBUF port map ( I => c, O => cbuf );

process(a,b)
begin
c <= a and b;
d <= a and b;
end process;

end mode_arch;

End of Record #3234 - Last Modified: 01/03/00 11:01

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