Answers Database
M1.4 Map - Timespec'ing RAMS (dualport) to FFS only covers SPO path.
Record #3243
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.4.
Problem Title:
M1.4 Map - Timespec'ing RAMS (dualport) to FFS only covers SPO path.
Problem Description:
When using the TIMEGRP constraint in a UCF to constrain the paths between the dual port RAMs and con
nected flops, only the F LUTs get referenced in the PCF. This only covers the SPO (associated with t
he FLUT) but not the DPO (associated with G LUT).
Notice the first TIMEGRP line contains only BEL "ram16d_spo", repeated
twice. The BEL's name "ram16d_spo" is based on the output SPO net. The
DPO net has the name "ram16d_dpo", so the TIMEGRP line was changed
like so:
TIMEGRP "RAMS(ram16d*)" = BEL "ram16d_spo" BEL "ram16d_dpo" BEL "ram16d_spo" ;
This works. TRCE now controls both SPO and DPO.
(Oddly PERIOD constraint will cover this.)
Solution 1:
This issued has been fixed in the mapper so that the correct .pcf
constraints are written. This fix is included in the current M1.4 Core
Applications patch available from the Xilinx Download Area:
Solaris: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt17.zip
End of Record #3243 - Last Modified: 08/18/98 17:51 | 
