Answers Database
M1.4 Map - Mapper unable to merge a RAM and Flop with opposite clock polarities
Record #3245
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.4.
Problem Title:
M1.4 Map - Mapper unable to merge a RAM and Flop with opposite clock polarities
Problem Description:
ERROR:x4kma:312 - The following symbols could not be constrained
to a single CLB: RAM16X1S symbol "HREG_1/BANK2/DELTA/RAM1" (output
signal=HREG_1/BANK2/DELTA/D0) FDCE symbol "HREG_1/BANK2/DELTA/FF1"
(output signal=HREG_1/OUT2D0) The clock signals are of opposite polarity. These symbols share the s
ame RLOC attribute value, which requires them
to be mapped to the same CLB.
Solution 1:
A fix for this merge problem is included in the current M1.4 Core
Applications patch available from the Xilinx Download Area:
Solaris: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt17.zip
End of Record #3245 - Last Modified: 08/18/98 17:53 | 
